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STRUCTURE PRODUCT SERIES TYPE PIN ASSIGNMENT BLOCK DIAGRAM PACKAGE Functions
Silicon Monolithic Integrated Circuit 7-Channel Switching Regulator Controller for Digital Camera
BDMWV
Fig.1 Fig.1 Fig.2
1.5V minimum input operating Supplies power for the internal circuit by using charge-pump circuit which outputs a voltage twice bigger than VBATvoltage. or a equal voltage as VBAT + VIN. Contains step-up converter(1ch), step-down converter(2ch), cross converter(1ch), configurable for step-up/step-down converter(1ch), with 59 step brightness controller for step-up converter(1ch). Contains 4FETs for the cross converter channel. 3channels contain transistor for synchronous rectifying action mode. 2channels contain FETs for the step-up converter. All channels contain internal compensation between inputs outputs of error amps. Contains sequence control circuit for ch1,2 and 4. Operating frequency 1.2MHz(CH1,3,4), 600kHz(CH2,5,6,7). Contains output interception circuit when over load. 2 channels have high side switches with soft start function, one channel has PMOS back gate control circuit. Thermally enhanced UQFN044V6060 package.(6mm x 6mm, 0.4mm pitch)
Parameter Symbol Voltage VBAT VHx14 HS67H VLx67 VIN IomaxLx1 IomaxHx2 IomaxHx3 IomaxHx4, Lx4 IomaxHS67 IomaxLx67 Pd Topr Tstg Tjmax Limit 0.37 0.37 0.37 0.320 -0.37 0.4 1.5 1.2 2.2 1.2 0.8 0.54 (*1) 25+85 55+150 +150 Unit V V V V V A A A A A A W
Absolute maximum ratings (Ta=25)
Power Supply
Power
Input
Voltage
O
u
t
p
u
t
C
u
r
r
e
n
t
P O S J
ow per tor unc
e a a t
r Dissipatio ting Temperatur ge Temperatur ion Temparetur
n e e e
(*1) Without external heat sink, the power dissipation reduces by 4.32mW/ over 25
Recommended operating conditions
Parameter Power Supply Voltage VREF Pin Connecting Capacitor VREGA Pin Connecting Capacitor SCP Pin Connecting Capacitor C+H to C+L connecting Capacitor Oscillator Oscillator Frequency (CH1,3,4) OSC Timing Resistor Symbol VBAT CVREF CVREGA CSCP CF fosc RT MIN 1.5 0.47 0.47 1.0 0.6 47 Limit TYP 1.0 1.0 1.2 62 MAX 5.5 4.7 4.7 0.47 1.5 120 Unit V F F F F MHz k
CH7 recommended operating conditions
Parameter Fixed H when determine brightness Fixed L when OFF Fixed H when setting brightness Fixed L when setting brightness Fixed H when EN start-up Fixed L before setting brightness Brightness setting time When start-up Symbol T(ON) T(OFF) T(H) T(L) T(EN) T(CLR) T(SET) MIN 65X1/fosc 65X1/fosc 420 420 5X1/fosc 5X1/fosc Limits TYP MAX 10000 10000 Unit [S] [S] [nS] [nS] [S] [S] [S]
63X1/fosc 2048X1/fosc
Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority.
REV. A
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Electrical characteristics Ta=25, VBAT=3V, RT=62k, STB16=3V,UPIC7=2.5V
Parameter Symbol MIN 5.2 4.5 Standard value TYP MAX 5.4 4.8 50 90 2.6 2.30 200 0.54 170 6 1.1 Units Conditions Io=1mA,, INV17=1.2V NON5= -0.2V Only for internal Current VBAT=2.5V, INV17=1.2V NON5= -0.2V CF=1F, VBAT=2.5V RT=62k Parameter Soft Start CH1,2,4 Soft Start Time CH3 Soft Start Time CH5 Soft Start Time CH6 Soft Start Time CH7 Soft Start Time Output Driver CH1 Highside SW ON Resistance CH1 Lowside SW ON Resistance CH2 LX21Pin Highside SW ON Resistance CH2 LX21Pin Lowside SW ON Resistance CH2 LX22Pin Highside SW ON Resistance CH2 LX22Pin Lowside SW ON Resistance CH3 Highside SW ON Resistance CH3 Lowside SW ON Resistance CH4 Highside SW ON Resistance CH4 Lowside SW ON Resistance CH6 NMOS SW ON Resistance CH6,7 Load SW ON Resistance CH5 Driver Output Voltage H Symbol Min 1.5 0.5 1.5 2.0 4.7 Standard value TYP MAX 2.5 1.5 2.5 3.0 5.7 3.5 2.5 3.5 4.0 6.7 Units Conditions
Charge Pump Circuit Output Voltage Vcpout1 (Regulated) Output Voltage ( X2 Step up) Vcpout2
V V kHz V V V mA V mV A V
Tss1,2,4 Tss3 Tss5 Tss6 Tss7
msec msec msec msec msec
RT=62k RT=62k RT=62k RT=62k RT=62k HX1=3V, CPOUT=5.4V CPOUT=5.4V HX2=3.0V, CPOUT=5.4V CPOUT=5.4V
Output Vcpro 35 Resistance Operating fcp 60 75 Frequency Minimum VBAT Vst1 1.5 Voltage Internal Regulator VREGA Output Voltage VREGA 2.4 2.5 Prevention Circuit of Miss Operation by Low voltage Input Threshold Voltage Vstd1 2.15 Hysteresis Width Vstd1 50 100 Short Circuit Protection Timer start Vtcinv 0.42 0.48 threshold voltage SCP Stand by Vssc 22 Voltage SCP Out Source Iscp 2 4 Current SCP Threshold Vscp 0.9 1.0 Voltage Oscillator Frequency fosc1 1.0 1.2 CH1,3,4 Frequency fosc2 0.5 0.6 CH2,5,6,7 Max Duty Dmax1d 1,3,4Step Down Max Duty Dmax1u 86 92 1,4Step Up Max Duty 5,6,7 Dmax2 86 92 Max Duty Dmax3 CH2 LX21 Max Duty Dmax4 86 92 CH2 LX22 Error AMP Input Biias Current IINV 0 INV Threshold VINV1 0.79 0.80 Voltage1 INV Threshold VINV2 0.99 1.00 Voltage2 INV Threshold VINV3 855 900 Voltage3 INV Threshold VINV4 570 Voltage4 INV Threshold VINV5 285 Voltage5 INV Threshold VINV6 135 Voltage6 INV Threshold VINV7 60 Voltage7 INV Threshold VINV8 15 Voltage8 Base Bias Voltage Vref for inverted Channel CH5 VOUT5 -6.09 OutputVoltage Line Regulation DVLi Output Current Ios 0.2 When shorted 600 300 150 75 30
Io=5mA VREGA Monitor
RON1P RON1N RON21P

480 260 160
720 390 240
m m m
INV monitor CH4
RON21N
130
200
m
Vscp=0.1V
RON22P
180
280
m
VOUT2=5.0V
RON22N RON3P RON3N RON4P RON4N RON6N RON67P Vout5H

PVCC5 -1.5
130 160 130 190 110 500 200
PVCC5 -1.0
200 260 200 290 170 800 300 1.0
m m m m m m m V V
CPOUT=5.4V HX3=3.0V, CPOUT=5.4V CPOUT=5.4V HX4=5.0V CPOUT=5.4V CPOUT=5.4V HS67H=3.0V CPOUT=5.4V IOUT5=50mA, NON5=0.2V, PVCC5=3V IOUT5=50mA, NON5=0.2V
1.4 0.7 100 96 96 100 96 50 0.81 1.01 945 630 315 165 90 45
MHz MHz % % % % % nA V V v v v v v v
RT=62k RT=62k Vscp=0V (1)
INV17, NON5=3.0V CH14 CH6, 7V CH7I CH7I CH7I CH7I CH7I CH7I NON5 resistor12k, 72k (2) CPOUT=1.55.5V Vref=0V
CH5 Driver Vout5L Output Voltage L Switch to configure step up/down
UDSEL4 Control Voltage Step down Step up
CPOUT x0.7
0.5
VUDDO VUDUP VSTBH1 VSTBL1 RSTB1 VUPIH VUPIL ISTB1 ISTB2 ISTB3 ISTB4 Icc1
400 7.0
CPOUT CPOUT x0.3
V V V V k V V A A A A mA
Step -down UDSEL4=CPOUT Step-up UDSEL4=0V INV17=1.2V, NON5=-0.2V, VBAT=3.0V
0 1.5 -0.3 250 2.05 0
STB16
STB control Voltage Active Non Active
5.5 0.3 700 4.0 0.4 5 5 5 5 11.0
Pull down Resistance UPIC7
UPIC7 control Voltage Active Non Active VBAT terminal HS67H terminal HX terminal LX terminal
Circuit Current
-6.00 4.0 1.0
-5.91 12.5
V mV mA
Stand-by Current
Circuit Current1 (VBAT current when voltage supplied for the terminal) Circuit Current2 (CPOUT current when voltage supplied for the terminal)
Icc2
3.0
5.0
mA
INV17=1.2V, NON5=-0.2V, CPOUT=5.4V
C+H, C+L=OPEN
(1)The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. (2)Recommend resistor value over 20k between VREF to NON5, because VREF current is under 100uA. (3)UPIC7 is not connected pull-down resistor. UPIC7 must input H or L level voltage when CH16 is active. This product is not designed for normal operation with in a radioactive environment
REV. A
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Pin Assignment Block Diagram
CPOUT VREGA VBAT VREF
33 32 31 30 29 28 27 26 25 24
INV1
23 REF 0.8V + + + +
PRE DRIVER
GND
NON5 INV6 INV7 INV7I UPIC7 HS6L HS67H HS7L Lx7 PGND567 Lx6
REF 0V 34 35 36 37 38
1.0V VREF + 2.5V REG
CHARGE PUMP
OSC
SCP
SCP
C+H
C+L
VIN
RT
UVLO TSD
REF + 1.0V REF + 1.0V +
REF 0.8V REF 0.8V REF 0.8V
B.G.CTL
22 21 20 19 18 17 16
INV3 INV2 INV4 Hx4 Lx4 PGND4 Hx2 Lx21 PGND2 Lx22 VOUT2
DAC
OCP
39 HI-SIDE SW 40 41
OCP
PWM & LOGIC BLOCK
PRE D RIVER
OCP
15 14 13
42 43 44 PRE DRIVER PRE DRIVER PRE DRIVER
400k 400k
PRE DRIVER
PRE DRIVER 12
400k
1
2
3
4
5
6
7
8
9
10
11
STB56
STB124
PGND13
UDSEL4
OUT5
PVCC5
STB3
Lx1
Hx1
Lx3
Hx3
Fig. 1
Package
Pin Description
Pin Name VBAT VIN CPOUT GND Description Input for battery voltage Returning voltage from output terminal Output terminal for Charge Pump Ground terminal Terminal for connecting flying capacitor for Charge Pump(H side) Terminal for connecting flying capacitor for Charge Pump(L side) Ground terminal for internal FET VREGA output CH5 base bias voltage CH5 PMOS VCC input for driver Terminal for connecting gate of CH5 PMOS Input terminal for synchronous High side switch, Power supply for Pch Driver Terminal for connecting inductors Power supply for channel 2 Terminal for connecting inductor for CH2 input Terminal for connecting inductor for CH2 output CH2 output voltage Power supply for internal load switch Output terminal for internal load switch Error AMP inverted input Error AMP non-inverted input Error AMP inverted input For connecting a resistor to set the OSC frequency For connecting a capacitor to set up the delay time of the SCP Step-up/down switching mode selection(H: step-down, L:step-up) ON/OFF switch H: operating over 1.5V ON/OFF switch for CH7 brightness control
BD9351MW
C+H C+L PGND13,2,4,567 VREGA VREF PVCC5 OUT5 Hx1,3,4
LOT No.
Lx1,3,4,6,7 Hx2 Lx21 Lx22 VOUT2 HS67H HS6L,HS7L INV1,2,3,4,6,7 NON5 INV7I RT SCP UDSEL4 STB124,3,56 UPIC7
Fig. 2
REV. A
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Operation Notes
.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. .) GND potential Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must not have voltage below - 0.3V on start up. .) Setting of heat Make sure that power dissipation does not exceed maximum ratings. .) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. .) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. .) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. .) Voltage of STB pin The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V. The region between 0.3V and 1.5V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01F. .) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. .)Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. .)IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15): When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal.
Resistor Terminal A
Transistor (NPN) B Terminal B C
E GND Terminal Parasitic element N GND
P N N P-board
P
P N Parasitic element
P N
P P-board
P
Parasitic element
GND
Fig - 3 Simplified structure of a Bipolar IC
REV. A

N
Notice
Notes
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